Photonic Layout Engineer

Quantum is now, and it's built here.

Oxford Ionics, now part of IonQ, is pioneering the next generation of quantum computing. Using our world-leading trapped-ion technology, we’re building the most powerful, accurate and reliable quantum systems to tackle problems that today’s supercomputers cannot solve.

Joining Oxford Ionics means becoming part of a global IonQ team that is transforming the future of quantum technology - faster, at scale, and with real world impact.

What to expect:

We are looking for a Photonic Layout Engineer to join our QPU Design team at Oxford Ionics/IonQ. In this role, you will be responsible for the layout of photonic integrated circuits (PICs) that form a central part of our Quantum Processor Units (QPUs), the novel technology that sit at the heart of our quantum computers and contributes to the team’s mission of advancing the design of these high-performance chip. You will work closely with scientists, photonic design engineers and fabrication engineers to bring new designs for ion trapping chips into production.

You’ll play an important part in shaping the hardware that supports our work in building the world’s most advanced quantum systems.

What you'll be responsible for:

In this position, you will work on integrating photonic components into complex multi-layer chips. This work will support the effective delivery of devices that make use of on-chip light delivery to allow scaling to thousands of qubits and beyond. You will have the opportunity to accelerate the tape-out of new chips and drive the design workflow of integrated photonics, contributing directly to the success of building utility-scale quantum computers.

Key responsibilities include:

• Arranging and routing photonic components on chip, in coordination with metal track and CMOS routing.
• Producing reticle-size photonic layout files using Python scripts as part of tape-out of the full chip, suitable for use in a commercial foundry.
• Collaborating with scientists to discuss their requirements.
• Interfacing with photonic designers, test engineers, packaging engineers and fabrication engineers to define design rules and shape component design.
• Layout verification through DRC and LVS.
• Contributing to custom layout Process Design Kits (PDKs) that are specific to IonQ and the foundry.
• Documenting the layout process and the final tape-out mask files.