QPU Design Engineer
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- 1 location, On-site, Full time
- Current openings
- 12 active jobs
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- English
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- Collected from public career pages and reviewed through JobGrid.eu source availability checks. Last verified: May 13, 2026.
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Quantum is now, and it's built here.
Oxford Ionics, now part of IonQ, is pioneering the next generation of quantum computing. Using our world-leading trapped-ion technology, we’re building the most powerful, accurate and reliable quantum systems to tackle problems that today’s supercomputers cannot solve.
Joining Oxford Ionics means becoming part of a global IonQ team that is transforming the future of quantum technology - faster, at scale, and with real world impact.
What to expect:
We are looking for a QPU Design Engineer to join our Processor Design team at Oxford Ionics/IonQ. In this role, you will be responsible for integrating all the features required for the successful operation of our quantum computers into complex chips. You will be directly contributing to the team’s mission of advancing the design of high-performance quantum processing units, the novel technology that sits at the very heart of our quantum computers. You will work closely with scientists and fabrication engineers, understanding how the various parts of a chip influence and constrain each other, to bring new designs for ion trapping chips into production.
You will play an important part in shaping the hardware that supports our work in building the world’s most advanced quantum systems.
What you'll be responsible for:
In this position, your primary responsibility will focus on turning operational requirements into chip layout, supporting the effective delivery of devices that enable the use of new technologies. You will have the opportunity to expand the range of features supported by our chips, contributing directly to the success of building utility-scale quantum computers.
Key responsibilities include:
- Guiding the end to end chip design process, from requirements to layout and tape-out.
- Coordinating with other teams to ensure feasibility and compatibility between the various layers of the chip.
- Collaborating with scientists to discuss their requirements and settle on specifications.
- Laying out complex multi-layer chips, including metal track routing and interfaces with photonics and CMOS.