asteralabs

Principal Digital Design Engineer

🇺🇸 San Jose, United States On-site Engineering, Manufacturing & Construction Posted May 20, 2026
Location San Jose, United States
Workplace On-site
Salary USD 230,000+ / yearly
Language English
Posted May 20, 2026
Last verified May 29, 2026

Salary context for this role

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Listed salary

USD 230,000+ / yearly

Salary published on this job listing.

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Role summary by JobGrid

Principal Digital Design Engineer at asteralabs: San Jose, United States; On-site; Engineering, Manufacturing & Construction; USD 230,000+ / yearly. JobGrid adds normalized role facts, source context, and a path to the employer application page so candidates can compare the listing before applying.

  • Location and workplace: San Jose, United States, On-site
  • Role classification: Engineering, Manufacturing & Construction
  • Employer salary shown on the listing: USD 230,000+ / yearly
  • Source freshness: checked by JobGrid on 2026-05-29.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.

Job Description

We are looking for Principal Digital Design Engineers with experience developing micro-architecture and implementation of the front-end circuit design, including RTL, synthesis, IP integration, and block-level verification for high performance network controllers. The candidate must have good knowledge of communication/interface protocols such as PCI-Express (Gen-3 and above), Ethernet, Infiniband, DDR, NVMe, USB, etc.

Basic Qualifications:

  • Strong academic and technical background in electrical engineering. A Bachelor’s degree in EE is required, and a Master’s degree is preferred.
  • +8 years’ experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications.
  • Professional attitude with the ability to prioritize a dynamic list of multiple tasks, plan and prepare for customer meetings in advance, and work with minimal guidance and supervision.
  • Entrepreneurial, open-mind behavior and can-do attitude. Think and act fast with the customer in mind!
  • Authorized to work in the US and start immediately.

Required Experience:

  • Hands-on, thorough knowledge of high-speed protocols like PCIe, Ethernet, Infiniband, DDR, NVMe, USB, etc.
  • Proven front end design expertise – architecture, RTL, simulations, synthesis, timing closure, GLS, DFT etc.
  • Full chip or block level ownership from architecture to GDS, driving multiple complex designs to production
  • Experience with Synopsys and/or Cadence digital design tools/flows
  • Good knowledge of design for test (DFT), stuck-at and transition scan test insertion
  • Familiarity with UVM based design verification
  • Silicon bring-up and debug expertise
  • Small-geometry CMOS (≤28nm) design

Preferred Experience:

  • Firmware development with C-language, scripting with Python or other equivalent programming languages.
  • Development/support for PCIe or Ethernet Switch products.

The base salary range is $185,000.00 USD – $230,000.00 USD. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. 

We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.